Samsung explores new memory technology: vertically stacked above AI accelerators with a density ten times that of traditional HBM5.

Samsung Electronics has launched its V10 Bonding V-NAND, or BV-NAND prototype, at the Future Storage and Memory Conference held in Santa Clara, California. This chip features a structure with over 400 layers and employs a new wafer bonding architecture to enhance storage density and performance. Samsung stated that its BV-NAND technology improves storage density by about 58% compared to the previous generation V9 NAND, while also enhancing read, write, and input/output performance to meet the growing demand for higher capacity and more energy-efficient storage solutions in artificial intelligence systems. Samsung also showcased what it claims to be the industry's first zHBM and zNAND-O architecture concept models. This technology stores more data in smaller spaces by vertically stacking storage cells. Unlike traditional HBM that packages alongside AI processors, Samsung's zHBM stacks memory vertically above the AI accelerator to reduce data transfer distance, increase bandwidth, and improve energy efficiency. Samsung indicated that its wafer bonding technology is expected to achieve storage density more than 10 times that of traditional HBM5 memory, while tripling energy efficiency and reducing thermal resistance by more than half.