Guangzhou: Actively developing advanced packaging technologies such as wafer-level, system-level, fan-out, flip-chip, silicon through-hole, Chiplet heterogeneous integration, and three-dimensional packaging.

date
13/01/2026
The Guangzhou Municipal Bureau of Industry and Information Technology openly solicits opinions on the "Guangzhou Policies on Promoting High-Quality Development of the Integrated Circuit Industry throughout the Thirteenth Five-Year Plan Period". It mentions actively developing advanced packaging technologies such as wafer-level, system-level, fan-out, flip-chip, silicon vias, Chiplet heterogeneous integration, three-dimensional packaging, as well as advanced wafer-level testing technologies like pulse sequence testing, MEMS probes, and IC integrated probe cards. The policy aims to accelerate the upgrading of packaging testing process technologies and capacity, support the construction of advanced packaging testing production lines, and provide subsidies to eligible projects not exceeding 20% of the new equipment purchase amount, with a maximum of 20 million RMB per project. It encourages integrated circuit packaging and testing companies to increase investment in technological transformation and provides corresponding rewards for eligible investment projects in accordance with Article 4 of this policy.