Moore's Law lives on! IBM released the world's first 0.7 nanometer chip technology, ushering in the "Era of Amy" in the AI computing power revolution.

At the moment when the traditional process approaches the physical limit, IBM (IBM.US) has advanced chip nodes to 0.7 nanometers (7 angstroms) using a three-dimensional vertical stacking architecture, marking the official entry of the semiconductor industry into the atomic scale era. On June 25, IBM announced a milestone breakthrough in semiconductor technology, introducing the world's first "sub-1nm" chip manufacturing technology. This technology utilizes the revolutionary "NanoStack" transistor architecture, which directly advances the process node to 0.7 nanometers, or 7 angstroms. Boosted by this news, IBM's stock in the US surged more than 6% pre-market. As of the time of writing, IBM's pre-market gains have narrowed to 3.44%, reaching $272. Earlier this year, IBM's stock price had fallen by about 11.2%, and this rebound has recovered a significant portion of the losses. Technological breakthrough: From "nano sheets" to "nano stacking" NanoStack is a new transistor architecture developed by IBM researchers and the first known three-dimensional nano-sheet stacking design in the industry. Unlike traditional chips that mainly arrange transistors in a flat plane, NanoStack vertically stacks and interleaves transistors, using three-dimensional sequential integration technology to accommodate more transistors in the same area. The core breakthrough of this architecture includes: Doubled density: Integrating nearly 100 billion transistors on a chip the size of a fingernail, with density approximately double that of IBM's 2021 2-nanometer chip. Performance leap: Compared to 2-nanometer node chips, the new technology is expected to deliver up to a 50% increase in performance, or a 70% reduction in power consumption. SRAM breakthrough: Research presented at the VLSI 2026 conference shows that the NanoStack architecture can achieve a 40% area scaling for SRAM (static random-access memory) - significant for long-standing on-chip cache that has been difficult to shrink, especially fitting the demands of AI workloads for high-bandwidth data. The NanoStack design also allows for different material combinations in each stacking layer, optimizing the performance and power consumption of each transistor independently. IBM has successfully verified this through experiments with ultra-thin dielectric bonding in CMOS integration, demonstrating the operational function of CMOS inverters with the expected switching performance, confirming that the technology can be practically manufactured and support real computation. Jay Gambetta, Director of the IBM Research Lab and an IBM Fellow, said: "With the new NanoStack architecture, we are not just reducing the size of transistors, but fundamentally redefining how chips are built to achieve stronger performance and higher energy efficiency." "The 0.7 nanometer node is no longer an exact description of physical size, but a generational term for technology." - Industry analysts point out that the semiconductor industry has long moved away from the era of "node equals feature size." The real significance of IBM's breakthrough this time is that NanoStack allows logic chip technology to potentially enter sub-1nm nodes for the first time, moving chip miniaturization from the nanometer level to the angstrom level, entering the atomic scale domain. IBM stated that this breakthrough "lays the foundation for the next computing era." For the semiconductor industry facing traditional process physical bottlenecks, this provides a new path for continuing performance improvements. AI compute revolution: Training time shortened from months to weeks In another blog post, IBM pointed out that current mainstream AI accelerators can generate around 1500 TOPS (trillions of operations per second), while accelerators using 7 angstrom technology are expected to generate about 7000 TOPS, approximately seven times more than the former. If a 7 angstrom chip is used to train current large-scale language models (LLMs), the training time can be significantly reduced from about three months to weeks. IBM stated that the new technology will provide significantly stronger computational support for generative AI, cloud infrastructure, and next-generation electronic devices. Against the backdrop of the industry facing an AI compute gap and a power crisis, IBM's technology is a shot in the arm for large model vendors. Currently, the most popular AI accelerator chips on the market (such as NVIDIA Corporation's Blackwell series and various in-house ASICs) generally hover around 1500 TOPS per chip. Gambetta said, "With the new NanoStack architecture, we are not just manufacturing smaller transistors, but reinventing the way chips are made. This provides the ultimate physical solution for the surging compute power and high energy costs of the AI era." Production timeline and industry ecosystem IBM expects that NanoStack technology could enter mass production within the next five years at the earliest and support at least the semiconductor process development for the next ten years. It is worth noting that IBM does not have its own wafer fabrication factories, and its business model is more like architecture licensing - IBM designs transistor architecture, and partners are responsible for manufacturing. IBM has previously licensed chip technology to Samsung and Japan's Rapidus. However, as of now, IBM has not announced specific manufacturing partners for this technology. IBM's research facility in Albany, New York has completed experimental validation of this technology. The facility will introduce High-NA EUV lithography equipment developed by ASML. IBM is currently working with partners such as Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions to advance related process development. In addition, IBM recently announced plans to establish Anderon as an independently operated subsidiary, becoming the world's first wafer foundry specifically dedicated to quantum chip manufacturing. This move shows that IBM is actively expanding in both classical computing and quantum computing frontiers. Competitive dynamics: The "angstrom race" of Taiwan Semiconductor Manufacturing Co., Ltd. Sponsored ADR, Intel Corporation, and Samsung Although IBM once again takes the lead in cutting-edge semiconductor research and development (R&D), it is important to note that IBM has already exited the front line of chip wafer manufacturing and transformed into a pure technology research and licensing giant. Currently, the top player in the global chip foundry arena is Taiwan Semiconductor Manufacturing Co., Ltd. Sponsored ADR (TSM.US). Currently, Taiwan Semiconductor Manufacturing Co., Ltd. Sponsored ADR has begun mass production of 2-nanometer chip technology using the first-generation nanoplate transistors. The company is developing A16 (1.6-nanometer) and A14 (1.4-nanometer) technologies. The A16 process technology will use a super rail (SPR), originally planned for mass production in the second half of 2026 but now delayed to start production in 2027. The A14 process will adopt Taiwan Semiconductor Manufacturing Co., Ltd. Sponsored ADR's second-generation nanoplate transistor structure, with technical development proceeding as planned. Samsung has announced that its A16 angstrom CMOS technology will be mass-produced in the fourth quarter of 2026. Intel Corporation announced last week that its new 18A manufacturing process (1.8-nanometer chips) has entered the risk production stage, the testing phase before commercial production. Analysts point out that while IBM leads on a technological level with the NanoStack architecture, there is still a significant gap between laboratory validation and large-scale manufacturing - competitors already have mature manufacturing capabilities and customer relationships. Nevertheless, the significance of IBM's 0.7-nanometer technological breakthrough far exceeds one company's technological achievements. In the context of traditional chip miniaturization approaching physical limits, IBM has demonstrated that even as the feature size of chips gradually approaches atomic scale, continuous improvements in performance and energy efficiency are still possible. The nano-stacking architecture extends logic technology to below 1-nanometer nodes for the first time, ushering in the era of "angstrom-scale scaling." For the global semiconductor industry, this breakthrough provides a new path for continuing performance improvements. In today's exponential growth in AI compute demand, IBM's 0.7-nanometer technology is not just an engineering feat but also a declaration that Moore's Law is not yet at an end.