CICC: Chip and Network Lean Upgrade Continues to Favor Core Investment Direction such as Optical Communication.

CICC released a research report stating that the eighth generation self-developed AI chips TPU 8t and TPU 8i were officially released at the Google Cloud Next 26 conference. This is the first time since the birth of TPU that Google (GOOGL.US) has separated the training and inference chips for separate design, and introduced updated configuration schemes at the cluster networking end. The firm believes that the lean division of AI hardware infrastructure is expected to further improve the efficiency of training and inference of large models, and further enhance the "cost reduction in supply-increase in demand" "flywheel effect". From the perspective of the industry chain, the firm continues to be optimistic about core investment directions such as optical communication, custom chip services, storage, and wafer foundry. Key views of CICC: Chips and Storage: From the chip level perspective, the core increment of 8t is a more balanced computing unit design + native FP4 + TPUDirect RDMA/Storage, with the goal of truly "feeding full" the training cluster; while the core increment of 8i is 384MB on-chip SRAM + 288GB HBM + CAE, corresponding to the core purpose of reducing long context, multi-agent, MoE inference latency, the firm believes that the above complex chip architecture design requires process support from foundry partners. In terms of system storage, the content of this release mainly involves low latency access, and does not mention the expected pooling of DRAM in the previous market. Network: TPU connection solutions upgraded again, focusing on OCS and the Boardfly architecture adapted to AI inference scenarios For training, the TPU 8t single card scale-out bandwidth quadrupled, scale-up bandwidth doubled, the front-end Jupiter increased the usage of OCS, and the network hardware configuration was improved; for inference, TPU 8i in the scale-up Boardfly architecture brings an additional 1.25 times 1.6T optical module increment for the third layer OCS full connection. The firm believes that as a trend of the Agentic AI era, MoE increases the demand for low-latency communication, the Boardfly architecture is a scale-up solution tailored to AI inference, also increasing the ratio between optical modules and TPU, dispelling concerns that inference will reduce the proportion of communication (combined with relatively lower inference card costs). Looking ahead, in the AI ASIC architecture represented by Alphabet Inc. Class C, the firm believes that there will be more solutions with increased network investment ratio, and AI optical communication still has the potential to surpass the long-term direction of high beta. Risks: The ramp-up progress of TPU related chip production is lower than expected; AI model and application iteration progress is lower than expected.