IMW 2025: Many companies and experts share new technologies, Samsung outlines the future development map of storage.

GMTEight APP learned that at the recent "IMW 2025" event, Samsung Electronics detailed the evolution and future challenges of the next generation of DRAM and NAND flash memory. Looking back at the changes in storage technology over the years, both DRAM and NAND flash memory are facing many obstacles to further development. In the keynote speech, Samsung expressed a strong desire to explore solutions and push for continued technological progress. The conference attracted many global companies and experts to participate, who engaged in rich and in-depth discussions about the future of DRAM and NAND. For example, imec publicly revealed pure metal gate technology for the first time, helping to shrink the interlayer distance of 3D NAND flash memory to 30nm while ensuring reliability; KX demonstrated its multi-level coding technology, bringing new possibilities for high-speed random access of flash memory; Applied Materials also developed Si channel technology for rapid epitaxial growth of 3D NAND. At the recent "IMW 2025" event, Samsung Electronics discussed the evolution of next generation DRAM and NAND flash. In the DRAM section, Samsung first reviewed the evolution of DRAM units over the years. In the 1990s, the flat n-channel MOS FET was the standard for unit select transistors (unit transistors). However, as we entered the 21st century, short channel effects and leakage currents became impossible to ignore. A transistor structure that allows lateral (horizontal) miniaturization without shortening channel length was designed and used for DRAM unit transistors. With the continued shrinking of lithography technology, the area of DRAM units could be continuously reduced. At the same time, improvements were made to the layout of DRAM unit arrays in the 2010s. The size of DRAM units is compared based on design rules (or minimum feature size) "F: feature size". In principle, the smallest unit possible is 2F (vertical size) x 2F (horizontal size) = 4F2, but this is extremely difficult to achieve. In the 2010s, by improving the layout of DRAM unit arrays, the unit area was reduced from the traditional "8F2" to "6F2". Even with the same processing size, the unit area decreased by 25%. This "6F2" layout is still the standard for high-capacity DRAM use today. Attempts to achieve higher memory densities include 3D DRAM. By stacking longer DRAM units vertically (with a bitline at one end, a channel in the middle, and a capacitor at the other end), memory capacity can be increased. From this point on, we will briefly explain the introduction of NAND flash memory (hereafter abbreviated as "NAND flash memory"). NAND flash memory, which has been in practical use since the mid-1990s (planar NAND flash memory), has reached its limits in terms of density and miniaturization. Initially, memory capacity and density were mainly increased through miniaturization, but by the early 2010s, miniaturization had reached its limit. This is because, even with air gaps that are believed to have the highest insulation performance, interference between adjacent units (unit transistors) can no longer be suppressed, and the amount of charge that units can store has been reduced to a level where interference cannot be prevented. The breakthrough at that time (the means to overcome the limitations) was 3D technology. The unit string, which is the basic circuit of NAND flash memory, has been converted from the horizontal direction to the vertical direction. As a result, units can store.The amount of stored charge has greatly increased, and the interference between adjacent units has significantly decreased.In addition, the company has also successfully implemented "multi-value storage" as a standard specification using 3D NAND flash memory, which is difficult to achieve with traditional semiconductor memory, storing three bits of data in a single cell. By increasing the number of stacked unit transistors in vertical unit strings, the vertical unit string has rapidly increased in density and capacity. In the early 2010s, products had 32 layers. By the mid-2020s, it has developed to over 300 layers, approximately ten times the original height. In addition, the layout of stacking storage unit arrays on top of peripheral circuits (CuA: CMOS under Array) has been put into practical use, reducing silicon chip area. At the same time, 3D NAND flash memory faces challenges similar to its predecessor planar NAND flash memory. As stacking increases, the holes forming the unit string channel become deeper, making etching more difficult. To alleviate this problem, the insulation film between the gate (word line) and word lines of the unit transistor has gradually become thinner. This increases interference between adjacent units in the same unit string and reduces the amount of charge that can be accumulated. Furthermore, the spacing between the holes (storage holes) forming the unit string channel is gradually decreasing, aiding in increasing storage density. This increases interference between adjacent unit strings. To address this issue, attempts have been made to use a ferroelectric film in the charge-trap unit instead of the nitrogen oxide film (ONO) as the gate insulation film. The charge trap method determines the logic value (1 bit of "high" or "low") by accumulating charges (mainly conduction electrons) in the capture energy level of the ONO film. The logic value of the ferroelectric thin film is determined by the polarization direction, rather than by the charge. By using a ferroelectric film in the unit transistor, it is possible to achieve effects such as reducing programming voltage and suppressing threshold voltage fluctuations. Both of these help reduce interference between sectors. It has been confirmed at the unit level that "multi-value storage" can be supported, increasing the threshold voltage of the unit transistor from two values to eight values (3 bits) or 16 values (4 bits). Caption: Example attempt of applying a ferroelectric thin film to the NAND flash memory unit transistor. The leftmost image (a) is a cross-section image containing a ferroelectric film (Ferro) as an insulating film (via TEM). The center (b) is a cross-section image of the unit transistor incorporating the ferroelectric thin film into a cylindrical structure similar to NAND flash memory (TEM). The rightmost (c) shows the measurement results when the threshold voltage varies in 16 different ways (equivalent to 4 bits per unit). DRAM and NAND flash memory both face many challenges in their future development. Samsung mentioned only a part of these challenges in their keynote speech. I hope to find solutions to these and other problems, and hope for progress to continue. More technical sharing In the presentations, enterprises and experts from around the world shared extensively on the future of DRAM and NAND. For example, imec publicly announced for the first time a pure metal gate technology that can shrink interlayer distances to 30nm while ensuring the reliability of 3D NAND flash memory. Kioxia also shared its multilevel coding technology, which enables high-speed random access of flash memory. Applied Materials has developed a technology for fast epitaxial growth of Si channels for 3D NAND. In addition to 3D NAND, GLOBALFOUNDRIES will showcase embedded flash memory technology compatible with 28nm HKMG CMOS logic. They demonstrated a prototype of a 34Mbit embedded flash macro. In the "DRAM" field, the venture capital company NEO Semiconductor, which is developing 3D memory technology, will discuss 3D DRAM technology "3D X-DRAM," similar in structure to 3D NAND. Memory supplier Macronix International will showcase an improved 3D DRAM technology consisting of two horizontal word lines, one vertical bit line, and gate-controlled thyristors. Semiconductor Energy Laboratory (SEL) has manufactured a prototype 1M-bit 3D DRAM with stacked planar FET and vertical channel FETs. In the "ferroelectric memory" field, Micron Technology will discuss its material engineering technology for high-performance, long-lasting ferroelectric memory. Georgia Tech will describe a manufacturing process for non-volatile capacitors that enables lossless readout of ferroelectric capacitors. GLOBALFOUNDRIES will also discuss charge trapping issues in complementary FeFET memory embedded in CMOS logic. In the "resistive memory/cross-point" field, Tsinghua University will showcase a 3.75Mbit embedded resistive memory macro compatible with 40nm high-voltage CMOS processes. Additionally, Winbond International has developed AsSeGeS and GeN heterostructures, optimizing the performance of OTS selectors used in cross-point memory.